FPGA Engineer

Senior FPGA Engineer – Freelance

About the role

Our client is expanding an established hardware development team and is looking for a Senior FPGA Engineer to support the development of high-speed sensor data acquisition systems and dedicated multi-gigabit communication links.

This is a 12-month freelance opportunity for an experienced FPGA engineer who can become productive quickly and work independently within an established architecture. You will take ownership of RTL implementation, I/O and data paths, with a strong focus on timing, latency and reliable cross-domain behaviour.

The initial requirement is for 1-2 engineers, with an ASAP start or within one month. The role is based in Overijssel, with two days per week on-site.

Main responsibilities

• Design and implement FPGA functionality using RTL.
• Work with Intel/Altera FPGAs, ideally the Agilex family.
• Develop and maintain high-speed transceiver functionality and multi-gigabit communication links.
• Work with transceiver speeds from approximately 12.5 Gbps upwards.
• Design timing-critical RTL operating at 200 MHz and above.
• Monitor and optimise latency across the data path.
• Support sensor data acquisition and the transfer of data to a central system.
• Develop and maintain SPI interfaces, including interfaces to ADCs.
• Debug timing, clock-domain crossing and other FPGA-related issues.
• Support FPGA I/O and interface control.
• Contribute to architecture and specification discussions where required.
• Work independently within an established architecture and deliver with limited ramp-up time.

Requirements

• Several years of senior, hands-on FPGA engineering experience.
• Strong experience working with high-speed FPGA transceivers.
• Experience with Intel/Altera FPGAs, ideally Agilex.
• Proven experience with multi-gigabit communication links, ideally at 12.5 Gbps or above.
• Strong RTL design experience.
• Experience designing and achieving timing closure on FPGA designs operating at 200 MHz or above.
• Strong understanding of clock-domain crossing and timing challenges.
• Experience working with latency-sensitive data paths.
• Experience with SPI and ADC interfaces.
• Ability to read and understand hardware architecture and work closely with hardware engineers.
• Comfortable working independently and becoming productive quickly.
• Professional working proficiency in English.

The offer

• 12-month freelance contract.
• ASAP start, or within one month.
• 2 days per week on-site in Overijssel.
• Opportunity to work on high-speed sensor data acquisition and multi-gigabit communication technology.
• Senior-level position within an expanding hardware development team.
• Initial requirement for 1-2 engineers.

The strongest candidates will bring a genuinely senior FPGA background, particularly around high-speed transceivers, multi-gigabit data links and timing-critical RTL. Experience with Agilex or comparable Intel/Altera devices will be particularly relevant.

This role is less focused on advanced DSP or complex control-loop development. The core challenge is bringing together high-speed transceivers, robust RTL, timing closure, latency, I/O and sensor data acquisition within an established architecture.

If you have the relevant FPGA and high-speed transceiver experience and are available for a 12-month freelance engagement, apply below.