Role Overview
We are looking for a freelance Verification Engineer to join an SoC Verification team. The role focuses on IP and SoC verification, taking ownership of verification activities from testbench development through sign-off.
Key Responsibilities
- Develop and maintain SystemVerilog UVM testbenches
- Define and implement functional coverage models
- Ensure verification sign-off targets are met (coverage, testbench quality)
- Take end-to-end ownership of verification for complex IPs and SoCs
- Contribute to improvements in verification strategy and testbench architecture
- Debug and resolve complex verification issues
Required Skills & Experience
- Strong experience with SystemVerilog and UVM
- Solid understanding of common protocols such as AMBA, USB, and I3C
- Experience with scripting languages (Python, Perl, or Tcl)
- Good knowledge of functional coverage and code coverage
- Experience using industry-standard simulators and debug tools
- (e.g. Questa, VCS, Verdi)
- Familiarity with assertion-based verification; Formal Verification experience is a plus
- Experience with CI / automation tools (e.g. Jenkins)
- Strong problem-solving and debugging skills
- Able to work independently in a remote, fast-paced environment
- Clear communicator with a collaborative mindset
Nice to Have
- Experience with C / C++ for embedded CPU or SoC verification
- CPU verification experience
Qualifications
- 5+ years of relevant SoC verification experience
- Proven experience creating and executing verification plans for complex SoCs or subsystems